1. Field of the Invention
The invention relates to Code Division Multiple Access (CDMA) receivers, and more particularly to demodulation of CDMA signals.
2. Description of the Related Art
Because there are a variety of transmission paths in CDMA systems, differences of transmission paths induce different levels of delay and attenuation of CDMA signal. It is well known as multi-path effect. For example, closely transmission paths for an urban area and loosely rural transmission paths cause different levels of signal distortion. In addition, the relative motion between a transmitting side and a receiving side also causes transmission path alteration; the delay of signal is varied along the time.
To relieve signal distortion from multi-path effect, each receiving finger of a rake receiver tracks and despreads received CDMA signal. Each time tracking loop tracks delays of the CDMA signals received by each rake finger corresponding to each different transmission path. The CDMA signals are then sampled. When the transmission paths of received CDMA signals change, the time tracking loop must advance or retard sampling timings to obtain optimal samples of the CDMA signals.
FIG. 1 is a block diagram of a portion of a CDMA receiver 100. The CDMA receiver 100 includes a sampling module 102, a code generator 104, a despreader 106, and a sample selection loop 108. Since the received samples of the receiver 100 are over sampling, the sampling module 102 may need to do down-sampling to decrease the sampling rate to adapt for a chip rate before any further processing by the CDMA receiver 100. The code generator 104 generates a despreading code according to a code generation trigger signal generated by the sampling module 102. The despreader 106 demodulates the samples to obtain original data transmitted by a CDMA transmitter.
The sampling module 102 first samples a CDMA signal received by the CDMA receiver 100 to obtain a plurality of samples including a series of early samples, a series of on-time samples, and a series of late samples. The sample selection loop 108 selects a series of optimal samples from the early samples, the on-time samples, and the late samples with the time tracking loop. The early samples, the on-time samples, and the late samples are respectively despread by corresponding despreaders 112, 114, and 116 with corresponding despreading codes generated by the code generator 104 to obtain an early output signal, an on-time output signal, and a late output signal. Finally, an optimal sample decision module 110 selects the optimal samples among the early samples, the on-time samples, and the late samples, and notifies the sampling module 102 of the selection with a sampling timing adjustment signal according to the selection.
FIG. 2 is a block diagram of a portion of CDMA receiver 200 which includes a timing control module 202 for implementing the sampling module 102 of FIG. 1. The timing control module 202 generates sampling trigger signals for early samples, on-time signals, and late signals. A series of samples with high sampling rate is delivered to despreaders 204, 206, and 208. The despreaders 204, 206, and 208 respectively decimate the samples according to the sampling trigger signals to obtain the early samples, on-time samples, and late samples. The despreaders 204, 206, and 208 then respectively demodulate the early samples, on-time samples, and late samples with the corresponding despreading codes to obtain an early output signal, an on-time signal, and a late output signal. The code generator 210 generates the despreading codes for the despreaders 204, 206, and 208 according to the code generation trigger signals. The decimation and demodulation are further illustrated in FIGS. 3 and 4.
FIG. 3a to 3c show decimation and demodulation in despreaders with a decimation factor of 4. FIG. 3a shows normal decimation and demodulation in despreaders 204, 206, and 208. A series of samples with indices of −4˜15 are shown. Because the decimation factor is 4, the despreaders 204, 206, and 208 select one sample from every four samples according to the trigger of corresponding sampling trigger signals to obtain the early samples, the on-time samples, and the late samples. The enabling periods of the sampling trigger signals, corresponding to the early samples, the on-time samples, and the late samples, are respectively marked with letters “C”, “B”, and “A” in FIG. 3a. 
An advance-retard (AR) counter periodically resets to meet the requirement of the decimating factor of 4. If a sample with the AR counter index of 0 is selected as an on-time sample, samples with the AR counter indices of −2 (equivalent to index 2 of pervious period) and 2 are respectively selected as an early sample and a late sample. For example, the AR counter indices of the samples with samples indices of 6, 8, and 10 are respectively −2, 0, and 2. Thus, the timing control module 202 must respectively enable the sampling trigger signals, corresponding to the early samples, the on-time samples, and the late samples, whenever the AR counter index is 2, 0, and −2.
The timing control module 202 must generate the code generation trigger signals in time to trigger the code generator 210 to change the despreading codes. For example, the samples with indices 6, 8, and 10 are respectively sampled as an early sample, an on-time sample, and a late sample, and demodulated with a common despreading code 2 to obtain the corresponding early output signal, on-time output signal, and late output signal, respectively. Thus, the code generator 210 must respectively deliver the common despreading code 2 to the despreaders 204, 206, and 208 at the periods corresponding to the samples 6, 8, and 10 according to the code generation trigger signal.
FIG. 3b shows adjustment of decimation and demodulation in despreaders 204, 206, and 208 in response to a sampling timing adjustment signal indicating advancement. The sampling timing adjustment signal advances the timing of the on-time sampling and the late sampling. Thus, the despreaders 206 and 208 take the samples 7 and 9 as an on-time sample and a late sample. Accordingly, the code generation trigger signal is also advanced for a sampling period to trigger the code generator 210 for generating the despreading codes. Thus, the samples 6, 8, and 9 sampled as an early sample, an on-time sample, and a late sample in FIG. 3a are advanced as the samples 6, 7, and 9 in FIG. 3b. The early sample of sample 6, however, is not changed to the sample 5 because the sampling timing adjustment signal is enabled subsequent to appearance of sample 6. A sampling error therefore occurs to affect the generation of the early output signal, inducing wrong selection of an optimal sample in the optimal sample decision module 110.
FIG. 3c shows adjustment of decimation and demodulation in despreaders 204, 206, and 208 in response to a sampling timing adjustment signal indicating retardation. The sampling timing adjustment signal delays the timing of the on-time sampling and the late sampling. Thus, the despreaders 206 and 208 take the samples 9 and 11 as an on-time sample and a late sample. Accordingly, the code generation trigger signal is also delayed for a sampling period to trigger the code generator 210 for generating the despreading codes. Thus, the samples 6, 8, and 9 sampled as an early sample, an on-time sample, and a late sample in FIG. 3a are retarded as the samples 6, 9, and 11 in FIG. 3c. The early sample of sample 6, however, is not changed to sample 7 because the sampling timing adjustment signal is enabled subsequent to appearance of sample 6. A sampling error therefore occurs to affect the generation of the early output signal, inducing wrong selection of an optimal sample in the optimal sample decision module 110.
FIG. 4a to 4c show decimation and demodulation in despreaders with a decimation factor of 8. FIG. 4a shows normal decimation and demodulation in despreaders 204, 206, and 208. A series of samples with indices of −8˜32 are shown. Because the decimating factor is 8, the despreaders 204, 206, and 208 select one sample from every eight samples according to the trigger of corresponding sampling trigger signals to obtain the early samples, the on-time samples, and the late samples. The enabling periods of the sampling trigger signals corresponding to the early samples, the on-time samples, and the late samples are respectively marked with letters “C”, “B”, and “A” in FIG. 4a. If a sample with the AR counter index of 0 is selected as an on-time sample, samples with the AR counter indices of −5 (equivalent to index 3 of previous period) and 5 are respectively selected as an early sample and a late sample. For example, the samples 11, 16, and 21 are respectively sampled as an early sample, an on-time sample, and a late sample.
FIGS. 4b and 4c respectively show adjustments of decimation and demodulation in despreaders 204, 206, and 208 in response to sampling timing adjustment signals indicating advancement and retardation. The timing control module 202 receives the sampling timing adjustment signal advancing or retarding the sampling of the on-time samples and the late samples. Thus, the samples 11, 16, and 21 sampled as an early sample, an on-time sample, and a late sample in FIG. 4a are advanced as the samples 11, 15, and 20 in FIG. 4b and are retarded as the samples 11, 17, and 22 in FIG. 4c. The early sample of index 11, however, is not advanced or retarded as the sample 10 or the sample 12 because the sampling timing adjustment signal is enabled subsequent to appearance of sample 11. A sampling error therefore occurs to affect the generation of the early output signal, inducing wrong selection of an optimal sample in the optimal sample decision module 110.
Sampling errors of timing control module 202 of FIG. 2 are therefore induced and cause wrong selection of an optimal sample in the optimal sample decision module 110. Additionally, the despreaders 204, 206, and 208 for early samples, on-time samples, and late samples don not synchronously execute sampling action, and the obtained early output signal, on-time output signal, and late output signal are asynchronous, increasing the signal processing burdens and complicating system design. Thus, a solution the aforementioned problem is desirable for processing a CDMA signal.